1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit devices, and in particular, to the design of interconnections for those devices.
2. Description of Related Art
Interconnect design for modern integrated circuit devices, especially for microprocessors, involves many considerations to minimize noise, ensure proper signal timing and switching, and to optimize performance. Key among the factors which must be considered is the effect of parasitics on the quality of signals transmitted by the interconnect.
Capacitance and inductance have varying parasitic effects on signals depending on the frequency at which current and voltage are changing over the interconnect, as well as the effective width of the interconnect. Most microprocessor interconnects, for example, are very narrow and thus, have a relatively high resistance. At typical microprocessor operating frequencies, for higher resistance interconnects, the parasitic effect of inductance on the interconnect impedance has been relatively small in comparison to the resistive component of the interconnect impedance and thus, has not been a concern. Even for wider signal lines having lower resistances, the operating frequencies of microprocessors have typically been in a range in which resistance dominates the interconnect impedance characteristics such that inductive parasitics can be ignored.
However, as the clock rate of digital integrated circuit devices, such as microprocessors, continues to climb, the inductive reactance, especially for relatively low-loss interconnects, becomes a major component of the interconnect impedance leading to problems of noise, ringing and delays. This is because the inductive reactance of a circuit varies in direct proportion to signal frequency. With clock rates targeted to reach into the gigahertz range, the significant upper frequency components of the digital signal may be as high as 15 GHz. In this range, for low-loss interconnects, even taking into account the increased resistance and reduced inductance caused by the skin effect at high frequencies, the resistance may not be high enough to offset the increased inductive reactance.
Low-loss interconnects are interconnects such as power buses, clock trunks and signal buses, which have a relatively high effective width. For example, power buses are wide and thus, have a low resistance. At high frequencies, the noise in low-resistance interconnects arises because the inductive time constant (L/R) dominates the capacitive time constant (RC) of the circuit. The circuit in this case is the circuit defined by the low-resistance interconnect and one of a multitude of possible paths through the integrated circuit chip by which current through the interconnect returns to ground.
To alleviate this noise and preserve signal integrity, it is important to come as close as possible to critical damping. Critical damping is achieved when the inductive and capacitive time constants of the circuit, L/R and RC, are equal to each other such that the capacitive and inductive effects on a signal effectively cancel each other out. One approach to balancing the time constants in the above situation is to add a decoupling capacitor. Adding a decoupling capacitor can increase the RC time constant of the circuit to balance out the larger inductive time constant. However, it may be undesirable to add a decoupling capacitor due to space and/or cost constraints. Additionally, adding a decoupling capacitor may require several additional processing steps if an on-chip decoupling capacitor is required.
Another solution to approach critical damping is to reduce the inductive time constant by reducing the inductance of the circuit. The inductance of a circuit is determined by several factors, key among them being the area of the signal "loop" formed by the circuit being evaluated. In currently available integrated circuit devices, the interconnect inductance is difficult to control to the extent necessary because of difficulties in determining the area of the current loop including the interconnect.
This issue is further clarified in reference to FIG. 1. FIG. 1 illustrates a simplified example of a cross-section of an integrated circuit device. A low-resistance interconnect 11 is formed in a layer on a substrate 12 and is separated from the substrate 12 by an insulating layer 13, referred to as an interlevel dielectric (ILD), and possibly by other layers (not shown). The load 14 represents a unit or device on the integrated circuit device which receives a signal from the interconnect 11. As is well-known in the art, all current signals supplied to devices on the integrated circuit device, including those transmitted by the low-resistance interconnect of FIG. 1, must eventually return to ground.
In the example shown in FIG. 1, there are many possible paths over which the current may return to ground. For example, a signal transmitted by the interconnect 11 may return to ground through the substrate 12 as shown by the current path 15, and/or through a ground plane 16 on the backside of the substrate 12, and/or through any one or more of a number of other possible current paths in the integrated circuit device. Thus, the current return path may either be close to the interconnect 11, or far away, and multiple current return paths may be involved making the inductance of the circuit difficult to determine. Because the current return path is not well defined, the inductance and thus, the inductive reactance is difficult to control effectively.
Thus, it is desirable to be able to control the inductance of low-loss interconnect lines to approach critical damping such that signal integrity is preserved even at very high frequencies.